Current Openings at UST -Global for Malaysia and Bengaluru
Front End Verification Engineer:
· Bachelors in Electrical, Electronics and communications or Computer Science with 4+ years of experience.
· Experience in front end functional verification solid experience in Verilog and System Verilog simulation and verification using industry standard tools such as Questa/ModelSim
· Expertise in verification methodologies (UVM) utilizing constrained random stimulus, assertions, and functional/code coverage analysis
· Experience with OVM/UVM
· Exposure to Gate level simulations will be an added advantage.
· Working knowledge of scripting languages such as Perl, or Tcl
· Good communications and presentation skills, creativity in solving/debugging problems, and attention to detail .
· Need knowledge on communications protocols/ bus protocols.
· Experience with system performance modeling and verification
Drop your CV to ameeta.pradeep@sventl.com
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